| VDD (V) | 2.7 to 3.6 | | | Clock voltage (V) | 1.8 to 5.5 | | | Analogue voltage (V) | 1.4 to 5.5 | | | Operating temperature | –40°C to +85°C | | | Frequency tolerance | 5 ±23ppm | | | CLK clock cycle | 500ns | | | EEPROM program/erase cycle | 105 times | | | Write to EEPROM current consumption | 3mA max. | | | EEPROM access time | 10ms max. | | |
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