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A differential line driver and receiver that uses the LVDS (Low Voltage Differential Signalling) system to provide a low cost, high speed, low power data transfer solution.
The single CMOS differential line receiver is designed to support data rates in excess of 400Mbps (200MHz) and will accept differential voltages of 350mV, translating them to 3V CMOS output levels. Additional features include low power design (18mV @3.3V), support for open, short and terminated input fail-safe and interoperability with existing 5V LVDS networks.
The quad CMOS flow-through differential line driver is the complementary device to the line receiver, also featuring a data rate in excess of 400Mbps. The device will accept low voltage TTL/CMOS input levels and translate them to low voltage (350mV) differential output signals. In addition, the driver features low power dissipation (13mW @3.3V) and high impedance on LVDS outputs on power down.
- Achieves high data rate, low power and low EMI
- Less susceptibility to common mode noise
- Flow-through pinout simplifies PCB layout
- 3.3V Power supply design
- Receiver accepts small swing (350mV typ.) differential signal levels
- Interoperable with existing networks
- Industrial operating temperature range (–40°C to +85°C)
- Packaged in a SO-8 (receiver) and a SO-16 (transmitter)
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| Receiver | Driver | | |
Supply voltage min./max. | –0.3 to +4V | –0.3 to +4V | | |
Recommended supply voltage | +3.0 to +3.6V | +3.0 to +3.6V | | |
Input voltage min./max. | –0.3 to +3.9V | –0.3V to (VCC + 0.3V) | | |
Recommended input voltage | GND to +3.0V | - | | |
Output voltage | –0.3V to (VCC + 0.3V) | –0.3 to +3.9V | | |
Maximum operating frequency | 250MHz | 250MHz | | |
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